Specifications

Analog RF and IF

• 5.0 - 20.0 GHz transmit and receive (usable to 22 GHz)
• 5 - 9 dB receive noise figure
• 10 - 15 dBm output power
• low-IF design (160 MHz IF)
• TX output and TX/RX input/output (field replaceable SMA)

Digital

• 14-bit 160 MSPS A/D for receive
• 16-bit 160 MSPS D/A for transmit
• JESD204B interfaces
• Intel Cyclone 10 FPGA (85k - 220k logic elements)

Control and Data Transfer

• 10 gigabit Ethernet interface (SFP+)
• simultaneous full rate transmit and receive
• PPS and 10 MHz inputs for synchronization

Software

• C++ using boost::asio and boost::lockfree::spsc_queue (for data)
• API similar to UHD, commonly used calls map easily
• Currently supports Linux; Windows support in progress
• Python bindings planned
• GPL v3 licensing planned with GitHub repo

Power

• 12 V DC power input
• 22 W active, 16 W idle

Physical

• 9.4 inches (23.9 cm) long (including connectors)
• 4.1 inches (10.5 cm) wide
• 1.0 inches (2.4 cm) high